How is ADC channel mapping done on F2812?

For ADC, does Analog input block “f281x-Ain:0” already shift 4 bits (the generated code showed it is so), therefore, this block gives exactly what is input (analog) at the pin. Where can I find the info for the channel chart: for example Ain:0 is ADCINA0, etc. Also where can I find the chart for Analog output, e.g., Aout:0.. etc. I didn’t see the converted results are accurate. Maybe I miss something. I did read the readme instruction to put the input to analog pin and Vreflo.
Thank you for your help.

ADC channel mapping in VisSim

The following discussion holds for the F281x and F280x chip set.
VisSim channels 0-15 map onto the F28xx ADCRESULT0-15 registers. The ADCRESULTx registers are mapped to ADC inputs pins (ADCINAn,ADCINBn) via the ADCCHSELSEQ Sequence Control registers. By default, VisSim maps ADCINA0-ADCINA7 to ADCRESULT0-7, and ADCINB0-ADCINB7 to ADCRESULT8-15.
You can change the sampling order in VisSim by selecting the ADC Config... dialog, clicking "New" under "Channel Sampling Order", and entering a new comma separated list of channels to be sampled.

There is no analog output for the F2812, only digital outputs.

The F2812 was the first design of the 12-bit ADC unit and I seem to recall it had some problems with the on-chip Vref. The newer F280 parts are much better. You can also try to increase the ADC sample duration in the ADC Config... block. That can increase accuracy.

Channel Sampling Order

If I only need to sample 3 channels, say, channel 0,1,2; I deleted the rest channels, but it showed 0,0,0... once I click OK. Is there any way I can do this?

Could you also explain how to "use full scale value = 1(faster code gen)", and "use continuous conversion" (if I already chose T1 underflow for the sample trigger. Thanks.

Don't worry, VisSim handles channel count automatically

The channel count is set in ADCMAXCONV, which VisSim sets to automatically to the number of channels you use. There is no need to edit the channel sequence.

The ADC Config... option use full scale value = 1 means that VisSim will use the ADCRESULTn register directly in the generated code, shifted so that the result will range in value from 0 to a max of .99975. You must check for ADCST SEQ BUSY or ensure there is enough delay from the ADCSOC (Start Of Conversion pulse) to ensure the value is ready. If you don't check the use full scale value = 1 option, VisSim generates a call to a function which checks ADCST SEQ BUSY before reading the ADCRESULT reg. It also scales the value to a max reading of 3.3v to correspond to the Vref on the eZdsp.

Use Continuous Conversion means that the ADC sequencer will automatically restart the sampling sequence when it gets to the end. So in your example of ADC 0-2, after sampling chan 2, it will sample chan 0 on the next ADCSOC pulse. If you don't specify Use Continuous Conversion then VisSim will issue a SEQ RESET to restart the ADC SEQuence at the start of the control timer interrupt. The next three ADCSOC pulses cause the ADC to sample ADCINA0, ADCINA1, ADCINA2, then stop (further ADCSOC pulses are ignored) until the next SEQ RESET is issued.