How are ADCCLK, main sample clock and EOC related?

In your DRV8312 sensorless FOC PMSM example it looks like PWM period=3000, ADCCLK=10MHZ and ADC is triggered at every 12 sample clock and motor algorithm is controlled by ADCINT1 at EOC9. I don’t get on what basis ADCCLK, sample clock and EOC has to be considered. How are they related. In our algorithm, Timer Period=2000, ADC CLK=80MHz, sample CLK=7 clock cycles and Controller loop is interrupted based on TIMER0. Is this right? A1,A5 are ADC channels where Left Motor currents are read and B1 and B5 are for right motor current calculation. If I have make left motor drive part of ADC interrupt handler, I consider ADCINT1 but at what EOC? And for right motor drive what ADC interrupt handler and EOC has to be considered.

Good question. The key is

Good question. The key is that the ADC is not triggered every 12 ADCCLKs, it has a 12 ADCCLK sample duration (or whatever sample duration you choose). The sample duration depends on the impedance of the sensed signal. The higher the impedance, the longer you will need to sample to obtain a low noise sample. The trigger, in the case of our DRV8312 sensorless FOC diagram, is ePWM SOCA. The ePWM is set up to send SOCA when there is current flowing through the shunt resistor. Since the PWM is using up/down count mode, the effective period is 6000, so if TBCTR=period is the SOC event, you will generate a SOC every 6000 ticks which results in a 10kHz SOC rate on a 60MHz part. This 10kHz SOC rate translates to 10 kHz execution rate of the ADC EOC interrupt handler compound block in VisSim. The rest of the VisSim diagram will be executed under the control interrupt rate which is set in the *System Properties..." screen. Normally the main diagram is executed under interrupt from timer 2, but you can set it to be any timer or PWM if you want.
As for which EOC to use in the interrupt handler, the ADC unit will service simultaneously triggered channels in round robin fashion starting with the lowest order channel and counting up. Since you want to take an ADC EOC (End of Conversion) interrupt after all channels have been sampled, you would use the last channel as EOC interrupt source. This would be EOC13 for you (assuming that you assign ADCRESULT regs to physical ADC pins). Then inside the VisSim compound block that handles the EOC interrupt you will know that A1,A5,B1,B5 have all been recently sampled (assuming that all 4 use the same SOCx trigger). Then you can put both motor drives under the same interrupt handler compound block. You could have two separate interrupt handlers by starting the 2nd motor ePWM counters at 1/2 period via the phase register, then use SOCx from the 2nd PWM to trigger B1,B5. However, there is little to be gained from this as you will now have twice the interrupt overhead (2 cache pipeline stalls, register set save/restore).